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- C 66.3%
- Assembly 33.1%
- Makefile 0.6%
a5b5d9b7f5* Cadence/Xtensa: NX bug-fixes for imprecise exception handling - Update NX init logic to check whether a software interrupt is already registered before provisioning it for the scheduler. - Add new xt_get_interrupt_handler() API to enable above fix. - Fix exception dispatch assembly code to correctly provide the exception stack frame to imprecise exception handlers (NX only). - Confirm functionality on windowed/call0 configs with and without FreeRTOS MPU support. Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: SMP support for Xtensa FreeRTOS - Merge pull request #2 from IPG-TIP-Xtensa/dev-xtensa-smp - Cadence/Xtensa: Add an assertion for SMP init ordering. - Cadence/Xtensa: Require RJ.5 tools - Cadence/Xtensa: SMP fixes to enable multicore Palladium - Cadence/Xtensa: Update coproc handling for SMP - Cadence/Xtensa: Limit outstanding CacheOps coming from L2 - Cadence/Xtensa: Update release notes for 3.10 release - Remove DRAM requirement - Call main() only for core 0 - Replicate/consolidate per-core intr/coproc data - Separate initial stacks per-core - Additional fixes and clean-up - Update release notes for 3.11 release - FreeRTOS/SMP: CP save bug-fix Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: SMP: Increase core 0 startup stack size - Extra space required for main() to call printf() without overflowing when argv[0] has a long path Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Enable context switch hooks for SMP builds - Enables xt_smp example to more accurately profile time taken in single vs. multicore test. Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Add multcore clib support to SMP port - Add per-core xclib reentrancy struct instances - Redefine reentrant pointer to __getreent() function via defining __DYNAMIC_REENT__ in xclib - Improve build infra to properly support overriding CFLAGS in nightly tests - Bump port rev to 3.12 Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Coprocessor handling fixes for SMP configs - Clear coproc owner thread when saving callee-saved state - Fix coproc init/release functions - Update readme and release notes Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Implement exclusive store locks for SMP - Removes dependency on XTOS locks - Clarify v3.12 release notes Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Clarify v3.12 SMP requirements - xclib is required for 3.12 Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Patch xtsubsystem.h - Resolve a couple of errors in <xtensa/xtsubsystem.h> when compiled with RJ.5 Xtensa toolchain and C++17. - Will no longer be necessary with RJ.6. Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Clear LCOUNT on ISR entry, new task creation - LCOUNT needs to be cleared during solicited context switch, ISR entry - Prevents incorrect zero-overhead execution - Extra conditional logic required for overlay save/restore Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Merge Xtensa v3.13 port into xtensa-dev Notes for Version 3.13 ---------------------- - FreeRTOS SMP support for newlib (experimental). - FreeRTOS SMP context switching performance improvements. - FreeRTOS SMP config option "XT_USE_L2RAM" moves data into L2RAM for context switching performance improvements. Disabled by default. - FreeRTOS SMP config option "XT_USE_DATARAM" moves per-core data into dataram for performance improvements. Disabled by default. - Based on FreeRTOS-Kernel V11.2.0 release in 3/2025. - Numerous fixes and improvements. Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Correct SMP patch include - Subsystem patch only required for RJ.5 tool-chain; do not apply for builds with earlier tools. Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Add support for idma-os library - Single-core multithreaded iDMA support - SMP iDMA support with pinned tasks - Example test and build infrastructure Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Fix race condition in idma-os module - NX configs were reallocating a channel before it was fully cleaned up Signed-off-by: Ian Thompson <ianst@cadence.com> * Cadence/Xtensa: Update release notes and readme - Xtensa port v3.13 tested and working with FreeRTOS-Kernel version 11.3.0. Signed-off-by: Ian Thompson <ianst@cadence.com> --------- Signed-off-by: Ian Thompson <ianst@cadence.com> |
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| .github | ||
| Cadence/Xtensa | ||
| CCRH | ||
| CCS/C2000_C29x_F29H85x | ||
| GCC | ||
| GHS/U2x | ||
| Tasking/AURIX_TC3xx | ||
| TI/CORTEX_A53_64-BIT_TI_AM64_SMP | ||
| LICENSE | ||
| README.md | ||
FreeRTOS Partner Supported Ports
This repository contains FreeRTOS ports supported by FreeRTOS partners. For a partner supported FreeRTOS port:
- The code has not been reviewed by the FreeRTOS team.
- FreeRTOS team has not verified the tests results but tests exist and are reported to be successful by the partner.
- Customer queries as well as bugs are addressed by the partner.
A new FreeRTOS port can be directly contributed by a partner. Follow the steps below to contribute a FreeRTOS port to this repository:
- Write the FreeRTOS port for your Compiler and Architecture.
- Create a project in the FreeRTOS Partner Supported Demos Repository for your hardware for running tests as mentioned here.
- Make sure all the tests pass. Add the test results in the Pull Request description.
- Add a README file with the following information:
- How to use this port?
- Link to the test project created in Step 2.
- Any other relevant information.
- Raise a PR to merge the FreeRTOS port.
- Raise another PR to merge the test project in the FreeRTOS-Partner-Supported-Demos Repository.
License
This repository contains multiple directories, each individually licensed. Please see the LICENSE file in each directory.